Embodiments of the present invention relate to a semiconductor device and a method for manufacturing the same, and more particularly to a semiconductor device including a vertical gate and a method for manufacturing the same.
As the integration degree of a semiconductor device increases, the channel length of a transistor gradually decreases. However, the reduction in channel length of the transistor may result in a Drain Induced Barrier Lowering (DIBL) phenomenon, a hot carrier effect, and other short channel effects, such as punch-through. In order to solve such problems, a variety of methods have been proposed, including for example, a method for reducing the depth of a junction region, a method for increasing channel length by forming a recess in the channel region of a transistor, and the like.
However, as the integration density of a semiconductor memory device, and more particularly, of a Dynamic Random Access Memory (DRAM), approaches Gigabits, it is necessary to manufacture a smaller-sized transistor. That is, a transistor of a gigabyte DRAM device requires a cell area of 8F2 or less (F: minimum feature size), and a cell area of about 4F2. Therefore, although the channel length may be scaled using a planar transistor in which a gate electrode is formed over a semiconductor substrate and a junction region is formed at both sides of the gate electrode, it is difficult to satisfy these size requirements. In order to solve the above-mentioned problem, a vertical channel transistor structure has recently been proposed.
However, a vertical channel transistor structure according to the related art causes a floating body effect in which a body is electrically separated from the silicon substrate by a source/drain junction region located at a lower end of a vertical gate as the line width of the device is reduced. If the floating body effect occurs, the cell threshold voltage of the transistor is lowered by a hole over the body, which results in deterioration of the refresh properties of the semiconductor device.